1. Field
The embodiments relates to a level shift circuit for use in a semiconductor device operated by a plurality of power supply voltages.
2. Description of the Related Art
In recent years, semiconductor devices are required to operate with less power consumption. To reduce power consumption in a semiconductor device, an internal circuit in the semiconductor device is configured to process a signal having a lower level than an external signal provided to the device. In other words, the internal circuit is operated by a power supply voltage having a level that is lower than the level of a signal used in an external device. A level shift circuit for converting a signal level between the level for an external device and the level used for an internal circuit is used in an input circuit and an output circuit of the semiconductor device.
In the prior art, a level shift circuit used as an output circuit is supplied with a first power supply voltage and a second power supply voltage, which is higher than the first power supply voltage. The level shift circuit converts the signal level of an internal circuit operated by the first power supply voltage to the signal level of the second power supply voltage. When the level shift circuit is supplied with the first and second power supply voltages at different timings, the level shift circuit may function erroneously and cause the flow of through current. To prevent such flow of through current, various types of level shift circuits have been proposed.
For example, Japanese Laid-Open Patent Publication No. 2003-17996 (FIG. 1) describes a level shift circuit including capacitors C1 and C2 and transistors N3 and N4. The level shift circuit determines the gate voltage of each of the transistors N3 and N4 with the capacitors C1 and C2 when supplied with a high power supply voltage and determines the logic value of a signal VOUT. This prevents the flow of a through-current.
Japanese Laid-Open Patent Publication No. 9-135160 (FIG. 1) describes a semiconductor device including transistors 146 and 147 arranged between a high-voltage side circuit block and a low-voltage side circuit block. The semiconductor device forcibly clamps an input level when the low voltage power supply is cut. This prevents the flow of a through-current.
Japanese Laid-Open Patent Publication No. 5-315931 (FIG. 1) describes a level shift circuit including a detection circuit. In a state in which the level shift circuit is being supplied with a high power supply voltage and a low power supply voltage, the detection circuit detects abnormalities in the low power supply voltage. When detecting an abnormality in the low power supply voltage, the detection circuit turns off a transistor QP1 and cuts the power supply. This prevents the flow of a through-current. Further, the detection circuit turns on a transistor QN1 to clamp the input potential at an inverter circuit 4. This prevents abnormal functioning of the level shift circuit.